VHDL

 

Finite State Machine Design

1) NOT Gate

 

library ieee;
use ieee.std_logic_1164.all;
ENTITY not 1 IS 
	PORT(x:IN STD_LOGIC;
		F:OUT STD_LOGIC;
	);
END not1;
ARCHITECTURE behv1 of not1 IS
BEGIN
	PROCESS(X)
	BEGIN
		IF(X==’1’) THEN
		F<=’0’;
		ELSE
		F<=’1’;
		ENDIF;
	ENDPROCESS;
END behv1;

 

---

2)OR Gate

 

Library ieee;
use ieee.std_logic_1164.all;
ENTITY or2 IS 
PORT (x,y:IN STD_LOGIC;
	F:OUT STD_LOGIC;
);
END or2;

 

ARCHITECTURE behv1 OF or2 IS
BEGIN
process(x,y)
BEGIN
IF ((X=’0’) AND (Y==’0’) )THEN
F<=’0’;
ELSE
F<=’1’;
ENDIF;
END process;
END behv1;

 

---

3)AND Gate

 

Library ieee;
Use iee.std_logic_1164.all
ENTITY and2 is
PORT (x,y :IN STD_LOGIC;
	F: OUT STD_LOGIC
);
END and 2;
ARCHITECTURE behv1 OF and2 IS
BEGIN
IF((x==’1’) AND (Y==’1’)) THEN
	F<=’1’ ;
ELSE 
	F<=’0’;
END IF ;
END PROCESS;
END behv1;

 

---

4)XOR Gate

 

Library ieee;
Use iee.std_logic_1164.all
ENTITY xor2 is
PORT (x,y :IN STD_LOGIC;
	F: OUT STD_LOGIC
);
END xor 2;
ARCHITECTURE behv1 OF xor2 IS
BEGIN
IF((x==’0’) AND (Y==’0’)) THEN
	F<=’0’ ;
ELSE  IF ((X=’1’) AND (Y==’1’)) THEN
	F<=’0’;
ELSE
	F<=’1’;
END IF ;
END PROCESS;
END behv1;

 

---

5) From the figure, write VHDL:

 

--component 1
Library ieee;
Use iee.std_logic_1164.all
ENTITY or2 is
PORT (x,y :IN STD_LOGIC;
	F1: OUT STD_LOGIC
);
END or2;
ARCHITECTURE behv1 OF or2 IS
BEGIN
Process(x,y)
IF((x==’0’) AND (Y==’0’)) THEN
	F1<=’0’ ;
ELSE 
	F<=’1’;
END IF ;
END PROCESS;
END behv1;
--component 2
Library ieee;
Use iee.std_logic_1164.all
ENTITY and2 is
PORT (A,B :IN STD_LOGIC;
	F2: OUT STD_LOGIC
);
END and2;
ARCHITECTURE behv1 OF and2 IS
BEGIN
Process(A,B)
BEGIN
F2<=A AND B;
END PROCESS;
END behv1;
--Top level circuit
Library ieee;
Use iee.std_logic_1164.all
Use work.all
ENTITY comb_ckt is
PORT (i1,i2,i3 :IN STD_LOGIC;
	O: OUT STD_LOGIC
);
END cmb_ckt;
ARCHITECTURE behv OF comb_ckt IS
Component end2 IS
PORT(A,B:IN STD_LOGIC;
F2 : OUT STD_LOGIC;
);
END COMPONENT;
Component or2 IS
PORT(X,Y:IN STD_LOGIC;
F1: OUT STD_LOGIC;
);
END COMPONENT
SIGNAL wire:STD_LOGIC
BEGIN
Gate1: and2 PORT MAP (A=> i1,B=>i2,F2=>wire);
Gate2: or2 PORT MAP (x=> i1,y=>i2,F1=>wire);
End behv;

 

---

6)MUX

 

ENTITY mux IS
PORT(I3,I2,I1,I0:IN STD_LOGIC_VECTOR(2 DOWNTO O)
S:IN STD_LOGIC_VECTOR (1 DOWNTO 0)
O:OUT STD_LOGIC-VECTOR (2 DOWNTO 0);
);
END mux;
ARCHITECTURE behv OF mux IS
BEGIN
	Process(I3,I2,I1,I0,S)
BEGIN
	CASE S IS
		WHEN “00” => O<=I0;
		WHEN “01” => O<=I1;
		WHEN “10” => O<=I2;
		WHEN “11” => O<=I3;
		WHEN OTHERS => O<=”zzz”;	
		END CASE;
END PROCESS;
END behv;

 

---

7) Decoder

 

ENTITY decoder IS
PORT(I:IN STD_LOGIC_VECTOR(1 DOWNTO 0)
O:OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
);
END decoder;
ARCHITECTURE behv OF decoder IS
BEGIN
	Process(I)
BEGIN
	CASE I IS
		WHEN “00” =>0 <=”0001”
		WHEN “01” => 0<=”0010”
		WHEN “10” => 0<=”0100”
		WHEN “11” => 0 <=”1000”
		WHEN OTHERS => O<=”zzz”;	
		END CASE;
END PROCESS;
END behv;

 

---

8) ADDER

 

ENTITY adder IS
GENERIC (N:natural :=2);
PORT(A,B:IN STD_LOGIC_VECTOR(n-1 DOWNTO 0);
C:OUT STD_LOGIC ;
S:OUT STD_LOGIC_VECTOR (n-1 DOWNTO 0);
);
END adder;
ARCHITECTURE behv OF adder IS
SIGNAL temp: STD_LOGIC_VECTOR (n DOWNTO 0);
BEGIN
	Temp <= (‘O’ & A ) + (‘O’ & B );
	S<= temp(n-1 DOWNTO 0 );
	C<= temp(n) ;
END behv;

 

---

9) calculate gcd

 

Library ieee;
Use iee.std_logic_1164.all
Use iee.std_logic_unsigned.all
Use iee.std_logic_arith.all
ENTITY gcd IS
PORT(clk,reset:IN STD_LOGIC);
A,B:IN UNSIGNED (3 DOWNTO 0);
G:OUT UNSIGNED (3 DOWNTO 0);
);
END gcd;
ARCHITECTURE behv OF gcd IS
TYPE state IS (idle,init,check,update_x,update_y,get_result);
SIGNAL pr_state:state := idle;
SIGNAL n_state ;
SIGNAL start:STD_LOGIC := ‘1’;
BEGIN
Sequential : process(clk,reset) IS
BEGIN
IF(reset==’1’) THEN
pr_state<= idle ;
ELSE  IF(clk==’1’)THEN
	pr_state <=n_state;
END IF ;
END process sequential
Combinational : process(pr_state ,A,B ) IS
Variable tempx,tempy:UNSIGNED(3 DOWN TO 0):= ‘0000’;
BEGIN
Case pr_state IS
WHEN idle=>
IF(start==’1’) THEN
n_state<= init ;
start <= ‘0’
ELSE 
	n_state <=idle;
END IF ;
WHEN init=>
tempx <=A;
tempy<= B;
n_state <=check;
when check=>
IF(tempx == tempy) THEN
n_state<= get_result ;
ELSE  IF (tempx>tempy) THEN
	n_state <=update_x;
ELSE
	n_state <= update_y;
END IF ;
WHEN update_x=>
tempx =temp_x - tempy;
n_state =>check;
WHEN update_y=>
tempy =tempy - tempx;
n_state =>check;
WHEN get_result=>
G =temp_x ;
n_state =>idle;
start <=’1’ ;
END CASE ;
END process combinational
END behv;

 

---

10) Sequence detector for string “1101” that outputs 1 when input matches the string

 

Library ieee;
Use iee.std_logic_1164.all
Use iee.std_logic_unsigned.all
Use iee.std_logic_arith.all
ENTITY seq_dat IS
PORT(X:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
clk:IN STD_LOGIC;
Y:OUT STD_LOGIC;
reset:IN STD_LOGIC;
);
END seq_dat;
ARCHITECTURE behv OF seq_dat IS
TYPE state IS (idle,init,check,pos_out,neg_out);
SIGNAL pr_state:state := idle;
SIGNAL n_state ;
SIGNAL start:STD_LOGIC := ‘1’;
BEGIN
Sequential : process(clk,reset) IS
BEGIN
IF(reset==’1’) THEN
pr_state<= idle ;
ELSE  IF(clk==’1’)THEN
	pr_state <=n_state;
END IF ;
END process sequential
Combinational : process(pr_state ,X ) IS
Variable tempx:STD_LOGIC_VECTOR(3 DOWN TO 0);
BEGIN
Case pr_state IS
WHEN idle=>
IF(start==’1’) THEN
n_state<= init ;
start <= ‘0’
ELSE 
	n_state <=idle;
END IF ;
WHEN init=>
tempx <=X;
n_state <=check;
when check=>
IF(tempx == ‘1101’) THEN
Y<= ‘1’ ;
ELSE
Y<= ‘0’;
END IF ;
n_state =>idle;
start <=’1’;
END CASE
END process combinational
END behv;

 

---

11)T-flip flop

 

Library ieee;
Use ieee.std_logic-1164.all;
ENTITY t_ff IS
PORT(T: IN STD_LOGIC;
clk: IN STD_LOGIC;
Q: OUT STD_LOGIC;)
END t_ff ;
ARCHITECTURE behv of t_ff IS
SIGNAL tmp:STD_LOGIC;
BEGIN
Process(clk)
BEGIN
IF CLK = ‘1’ THEN
IF T=’0’ Then
Tmp <= tmp ;
ELSE
Tmp <= NOT(tmp);
END IF;
END IF;
END PROCESS;
Q<=temp ;
END behv;