|Notice: Exam Form BE IV/II & BAR V/II (Back) for 2076 Magh|
|Routine: BE IV/II & BAR V/II - 2076 Magh|
|Result: BCE I/II exam held on 2076 Bhadra|
|Result: All (except BCE & BEI) I/II exam held on 2076 Bhadra|
|Notice: Exam Center for Barrier Exam (2076 Poush), 1st Part|
|Electronics and Communication(BEX)|
Basic Architecture of Software Design and Operation
- It consists of general datapath.
- Control unit does not store algorithms
- Algorithm is programmed into memory.
1. Fetch Instruction: It gets the next instructions as indicated by location in memory pointed by PC and stores into IR.
2. Decode Instruction: It determines the actual operations performed by the instructions at IR.
3. Fetch Operands: It gets the operand data needed for instruction from memory to appropriate registers of datapath.
4. Execute: The actual arithmetic or logical operations is performed by moving data through ALU.
5. State Results: It writes the data from datapath register into memory .
- Pipelining is the mechanism to increase instruction throughput of a microprocessor. It assumes the independent operations to be performed simultaneously.
- Superscalar microprocessor executes two or more scalar operations in parallel and requires two or more ALU.
- VLIW (Very Long Instruction Word) architecture is a static superscalar microprocessor that encodes several operations in single machine instructions.
- Programmer does not need detailed understanding of architecture. They just need to understand which instructions can be executed. Generally there are two levels of instructions assembly level and structured languages.
- Instruction set is the legal set of instructions that can be processed by a processor.
- Addressing modes indicates how the data for any operation is referenced in the instruction.
1. Program and data memory space
3. Input Output (I/O)
5. Operating System
1. Development processor: the processor on which programs are written.
2. Target Processor: The processor that will run the program.
3. If Development and target processor are different , the code can be run by downloading to target processor or by simulation.
4. Simulation can be done by using HDL and Instruction set simulator(ISS)
Software development process
The software development cycle is shown in given diagram:
Application Specific Instruction Set Processor
ASIP is the processor targeted for a particular domain. This architecture is domain specific but can be programmed .
For example Microcontroller , Digital Signal Processor
Selecting a Microprocessor
1. Speed (Clock speed or Instructions per second)
2. Power Requirements
3. Size (Power and data memory space)
4. Cost of Microprocessor
5. Development environment
6. Technical Support