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Notes of Embedded System [CT 655]



Communication Basics

-Bus is a set of wires with single functions within a communication
-Protocol describes the rules for communicating within a bus.
-Each sub protocol is called transaction or bus cycle
-Actor is a processor or memory involved in data transfer.
-Data direction indicates direction of transferred data.
-Address indicate where data should go to or come from.
-Control methods are schemes for initiating and ending the transfer.

Strobe Protocol

-The master uses one control line (request line) to initiate data transfer.
-The transfer is considered to complete after some fixed time.


Handshake protocol

-Master uses requet line to initiate transfer.
-The servant uses acknowledge line to inform master when data is ready.


ISA bus protocol

The timing diagram of ISA bus protocol is given below:


Microprocessor Interfacing: I/O Addressing, Interrupts and DMA

Port based I/O

-processor contains one or more N-bit ports.
-a port can be read or written directly by processor instructions.
-port are bit addressable (i.e. specific bit can be accessed)

Bus based I/O

-Memory is accessed using bus lines.
-Bus protocol is build within microprocessor
-A software does not implement this protocol.

Memory mapped I/o and standard I/O

-Peripherals occupy specific addresses in existing address space. In standard I/O bus includes M/IO to indicate whether the access is to memory or to a periphal.
-In memory mapped ,no special instructions are needed to communicate with peripherals.
-In standard I/O memory address is not lost.


1. Using fixed ISR location.

-up is executing the main program.
-peripheral (p1) receives i/p data and asserts int to request service
-After completing current instruction , up sees int. It saves PC and set PC to ISR fixed location.
-The ISR reads data and perform necessary functions . After P1 is read, P1 deasserts Int.
-The ISR returns and then PC is restored.

2. Using vectored interrupt

-when up sees int ,it saves pc and asserts inta.
-p1 detects inta and puts interrupt address vector on data bus .
-up jumps to address on the bus.

Direct Memory Access (DMA)

-up gives control of system bus to DMA controller.
-Up can execute its regular program./


Priority arbiter

The block diagram is shown below:


Daisy chain arbitration

The block diagram is shown below:


I^2C Protocol

-Inter –IC protocol
-Enable peripheral ICs to communicate.
-Data transfer rate upto 100kbits/s & 7-bit addressing (Normal)
-3.4 mbits/s & 10 bit addressing fast.


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