Digital Logic
Course Objective:
To introduce basic principles of digital logic design, its implementation and applications.
- Introduction (3 hours)
- Definitions for Digital Signals
- Digital Waveforms
- Digital Logic
- Moving and Storing Digital Information
- Digital Operations
- Digital Computer
- Digital Integrated Circuits
- Digital IC Signal Levels
- Clock wave form
- Coding
- ASCII Code
- BCD
- The Excess – 3 Code
- The Gray Code
- Digital Logic(1 hour)
- The Basic Gates: NOT, OR, AND
- Universal Logic Gates: NOR, NAND
- AND-OR-INVERT Gates
- Positive and Negative Logic
- Introduction to HDL
- Combinational Logic Circuits(5 hours)
- Boolean Laws and Theorems
- Sum-of-Products Method
- Truth Table to Karnaugh Map
- Pairs, Quads, and Octets
- Karnaugh Simplifications
- Don’t Care Conditions
- Product of Sums Method
- Product of Sums Simplification
- Hazards and Hazard Covers
- HDL Implementation Models
- Data Processing Circuits(5 hours)
- Multiplexetures
- Demultiplexetures
- Decoder
- BCD-to-Decimal Decoders
- Seven-Segment Decoders
- Encoder
- Exclusive-OR Gates
- Parity Generators and Checkers
- Magnitude Comparator
- Read-Only Memory
- Programmable Array Logic
- Programmable Logic Arrays
- Troubleshooting with a Logic Problems
- HDL Implementation of Data Processing Circuits
- Arithmetic Circuits(5 hours)
- Binary Addition
- Binary Subtraction
- Unsigned Binary Numbers
- Sign-Magnitude Numbers
- 2’s Complement Representation
- 2’s Complement Arithmetic
- Arithmetic Building Blocks
- The Adder-Subtracter
- Fast Adder
- Arithmetic Logic Unit
- Binary Multiplication and Division
- Arithmetic Circuits Using HDL
- Flip Flops(5 hours)
- RS Flip-Flops
- Gated Flip-Flops
- Edge-Triggered RS Flip-Flops
- Egde Triggered D Flip-Flops
- Egde Triggered JK Flip-Flops
- Flip-Flop Timing
- JK Mater- Slave Flip-Flops
- Switch Contacts Bounds Circuits
- Various Representation of Flip-Flops
- Analysis of Sequencial Circuits
- Registers(2 hours)
- Types of Registers
- Serial In–Serial Out
- Serial In–Parallel Out
- Parallel In–Serial Out
- Parallel In–Parallel Out
- Applications of Shift Registers
- Counters(5 hours)
- Asynchronous Counters
- Decoding Gates
- Synchronous Counters
- Changing the Counter Modulus
- Decade Counters
- Presettable Counters
- Counter Design as a Synthesis Problem
- A Digital Clock
- Sequential Machines(8 hours)
- Synchronous Machines
- Clock Driven Models and State Diagrams
- Transition tables, Redundant States
- Binary Assignment
- Use of Flip-Flops in realizing the models
- Asynchronous Machines
- Hazards in Asynchronous System and Use of Redundant Branch
- Allowable Transitions
- Flow tables and Merger Diagrams
- Excitation Maps and Realization of the models
- Digital Integrate Circuits(4 hours)
- Switching Circuits
- 7400 TTL
- TTL parameters
- TTL Overvew
- Open Collecter Gates
- Three-state TTL Devices
- External Drive for TTL Lods
- TTL Driving External Loads
- 74C00 CMOS
- CMOS Characteristics
- TTL-to–CMOS Interface
- CMOS-to-TTL Interface
- Applications(2 hours)
- Multiplexing Displays
- Frequency Counters
- Time Measurement
Practical:
- DeMorgan’s law and it’s familiarization with NAND and NOR gates
- Encoder, Decoder, and Multiplexer
- Familiarization with Binary Addition and Subtraction
- Construction of True Complement Generator
- Latches, RS, Master-Slave and T type flip flops
- D and JK type flip flops
- Ripple Counter, Synchronous counter
- Familiarization with computer package for logic circuit design
- Design digital circuits using hardware and software tools
- Use of PLAs and PLDs
References:
- Donald P. Leach, Albert Paul Malvino and Goutam Saha, “ Digital Principles and Applications”, 6th edition , Tata McGraw-Hill, 2006
- David J Comer “Digital Logic And State Machine Design” 3rd edition, Oxfored University Press, 2002
- William I. Fletcher “An Engineering Approach to Digital Design” Printice Hall of India, New Delhi 1990
- William H. Gothmann, “Digital Electronics, An Introduction to Theory and Practice”, 2nd edition, PHI, 2009
Evaluation Scheme:
The questions will cover all the chapters of the syllabus. The evaluation scheme will be as indicated in the table below
Chapters |
Hours |
Marks distribution* |
1 |
3 |
6 |
2 |
1 |
4 |
3 |
5 |
8 |
4 |
5 |
10 |
5 |
5 |
8 |
6 |
5 |
8 |
7 |
2 |
4 |
8 |
5 |
8 |
9 |
8 |
12 |
10 |
4 |
8 |
11 |
2 |
4 |
Total |
45 |
80 |
*Note: There may be a minor deviation in the marks distribution.
|